1. Field of the Invention
The present invention relates to a fabrication method for a bottom electrode of a capacitor. More particularly, the present invention relates to a fabrication method for a landing pad of a capacitor.
2. Description of the Related Art
As the density of integrated circuits increases, the formation of a contact node in the manufacturing of a capacitor usually employs a self-aligned contact window approach. Since the aspect ratio of the desired opening formed in the self-aligned contact window process is often too high, the quality of the etching is reduced and the etching conditions become more difficult to control.
FIGS. 1A and 1B are schematic, cross-sectional views of a self-aligned contact window showing the steps for manufacturing a self-aligned contact window according to the conventional methods.
Referring to FIG. 1A, a substrate 100 comprising an isolation layer 102, an etching stop layer 104 and a landing pad 106 is provided. A dielectric layer 108 is then formed covering the entire substrate 100, followed by forming bit line structures 110 and spacers 112 on the dielectric layer 108. The bit line structures 110 comprise a polysilicon layer 114, an adhesive layer 116 and a protective layer 118. Since the protective layer 118, for example, is a nitride layer and the dielectric layer 108, for example, is an oxide layer, the protective layer and the dielectric layer thereby exhibit a higher etching ratio. The adhesive layer 116, for example, tungsten or a tungsten silicide material, is used to enhance the adhesion between the polysilicon layer 114 and the protective layer 118.
As shown in FIG. 1B, an oxide layer 120 is formed, covering the entire substrate 100. Anisotropic etching is conducted, by means of a photolithography and etching technique, to remove the dielectric layer 108 and the oxide layer 120 above the landing pad 106. A contact window opening 122 is thus formed, exposing the landing pad 106. Since the position in forming the node contact window opening 122 is not completely aligned with the landing pad, the bit line structure 110 is etched. Since the bit line structure 110 includes the protective layer 118, the bit line structure 110 is protected from further etching by the protective layer 118.
The aspect ratio of the node contact window opening 122 formed by the above approach is, however, too high. The dielectric layer 108 and the oxide layer 120 in the node contact window opening 122 are thereby not completely removed (not shown in Figure), resulting in an incomplete exposure of the landing pad 106. Furthermore, although the protective layer 118 has a different etching ratio from the oxide material, it is more difficult to control the etching condition because the node contact window opening formed by this approach is too deep. If the etching condition is inappropriate or the etching period is too long, the protective layer is etched away and the adhesive layer 116 of the bit line structure 110 is exposed while forming the node contact window opening 122.